Floating point numbers are typically represented by a sign bit, an exponent, and a mantissa (also referred to as the significand) that contains the significant digits of the floating point number. For example, when representing a normalized floating point number in the IEEE Standard 754 for binary floating point arithmetic, the mantissa comprises an integer “1” and a fraction following a binary point.
The x87 architecture is a popular architecture for performing floating point arithmetic. The x87 architecture is described in the IA-32 Intel Architecture Software Developer's Manual, Volume 1: Basic Architecture, June 2006, which is hereby incorporated by reference in its entirety for all purposes (referred to herein as the “Intel manual”). In particular, section 4.8 describes the representation of real numbers in various floating point formats; chapter 8 generally describes programming with the x87 FPU; and section 5.2 describes the specific x87 floating point unit (FPU) instructions.
There are three different floating point formats that must be supported by an x87 FPU: single precision format numbers are 32 bits comprising a 1-bit sign, an 8-bit exponent, and a 23-bit mantissa; double precision numbers are 64 bits comprising a 1-bit sign, an 11-bit exponent, and a 52-bit mantissa; and double extended-precision numbers are 80 bits comprising a 1-bit sign, a 15-bit exponent, 1 integer bit, and a 63-bit mantissa. The precision of a floating point number is limited to the number of bits in its mantissa. Thus, given an implied integer ‘1’ bit to the left of the binary point in the single-precision and double-precision formats and the explicit integer ‘1’ bit to the left of the binary point in the double extended-precision format, the precision of a single precision format floating point number is limited to 24 bits, the precision of a double precision format floating point number is limited to 53 bits, and the default precision of a double extended-precision format floating point number is limited to 64 bits. However, the precision of calculations performed on double extended-precision format floating point numbers may be limited to less than 64 bits, and the precision limit is determined by the programmer. An x87 FPU includes a Precision Control (PC) field in its Floating Point Control Word (FPCW) that determines whether the precision of its floating point calculations are 64, 53, or 24 bits. A program may write to the PC field to change the precision of the x87 FPU floating point calculations. For example, if the program writes to the PC field to specify single precision, then the x87 FPU generates results with 24 bits of precision, even though one or more of the addends may have greater than 24 bits of precision. That is, the FPU rounds the mantissa of the result by clearing to zero the bits that are of less arithmetic significance than the precision specified by the PC field.
One common set of floating point arithmetic instructions executed by an x87 FPU are the addition (and subtraction) instructions. A floating point addition instruction performs the calculation of Ra+Rb, where Ra and Rb are floating point addends. The mantissa of Ra is denoted here as A, and the mantissa of Rb is denoted B. Assume Ra is the larger addend and Rb is the smaller addend, i.e., Ra has a larger exponent than Rb. The x87 FPU shifts B right by a number of bits equal to the difference between the exponents of Ra and Rb in order to align the mantissa of the smaller addend with the mantissa of the larger addend. The x87 FPU then adds mantissa A to the aligned mantissa B to generate a resultant sum. The FPU then normalizes the sum to remove any leading zeroes. Finally, the FPU performs a rounding operation on the normalized sum.
The rounding operation may be critical with respect to the timing of the execution of a floating point addition instruction by an x87 FPU. An FPU executes instructions according to a clock signal having a frequency and period. For a given semiconductor manufacturing process technology employed and FPU design (e.g., the number of gate delays required to execute the addition instruction), the clock period might have to be lengthened to accommodate the time to perform the rounding operation to execute the instruction. In the alternative, it is typical for an FPU to execute addition instructions in multiple clock cycles. In this case, it is desirable from a performance perspective for an FPU to execute floating point addition instructions in the smallest number of clock cycles possible given the clock period, the number of gate delays required by the FPU design to execute the instruction, the semiconductor manufacturing process technology employed, etc.
The rounding operation may be determinative of whether or not an additional clock cycle is required to execute a floating point addition instruction, i.e., whether the FPU can execute the floating point addition instruction in N clock cycles or N+1 clock cycles. This is because the rounding determination (i.e., whether the sum of the addends needs to be rounded up by incrementing) for an addition instruction by an x87 FPU depends upon the precision of the addends relative to the precision specified by the PC field of the FPCW. More specifically, the fact that the programmer could specify a precision via the PC field that is different than the precision of one or both of the addends could cause the rounding determination to take longer under some conditions than in others. There may be some conditions under which the longer time to make the rounding determination would cause the total execution time of the instruction to require an additional clock cycle. Thus, for example, whereas an x87 FPU could be designed to execute a floating point addition instruction in three clock cycles for a first set of conditions of the precision of the addends and the precision specified by the PC field, the FPU may require four clock cycles to execute the instruction for a second set of conditions of the precision of the addends and the precision specified by the PC field because the rounding determination takes longer for the second set of conditions. Following are some specific examples of conditions of the precision of the addends relative to the precision specified by the PC field and their affect on the rounding determination time.
If the precision specified by the PC field is the same as the precision of the addends, then only the smaller addend contributes bits to the rounding operation (referred to herein as sticky bits) due to the mantissa alignment discussed above. In this case, the rounding determination may be performed in parallel with the addition of the larger addend and aligned smaller addend by simply examining the sticky bits of the smaller addend, namely the number of least significant bits shifted right during the alignment operation. That is, the rounding determination time is mostly, if not all, hidden by the time taken to perform the actual addition of the two addend mantissas.
However, if the precision of the larger addend is greater than the precision specified by the PC field, then the larger addend may also contribute sticky bits to the rounding determination. In this case, the x87 FPU must add the sticky bits contributed by each of the two addends in order to make the rounding determination. The addition of the sticky bits may take as long as the addition of the non-sticky bits of the mantissa, i.e., the upper bits that are within the precision specified by the PC field. The x87 FPU subsequently examines the sticky bits sum in order to make the rounding determination after the addition of the mantissas. Importantly in this case, unlike the case in which only the smaller addend contributes sticky bits, the FPU cannot make the rounding determination in parallel with the addition of the larger mantissa and aligned smaller mantissa. Rather, the FPU must wait to make the rounding determination until the addition of the sticky bits has completed.
Much work has been done to perform fast floating point add operations. For example, see ON THE DESIGN OF FAST IEEE FLOATING-POINT ADDERS, Seidel, et al., IEEE Computer Society, Proceedings of the 15th IEEE Symposium on Computer Arithmetic (ARITH '01). However, this paper fails to take into account the requirements imposed upon a commercially-viable x87 FPU with respect to the ability of the programmer to specify the precision of floating point number calculations via the PC field. Specifically, the paper assumes that only one of the addends will contribute sticky bits to the rounding determination. However, as discussed above, the peculiarities of the x87 architecture, namely the PC field, can create situations where both of the addends contribute bits to the rounding determination. Depending upon factors such as the clock frequency of the microprocessor and the number of gate delays within the various circuits of the x87 FPU (e.g., adders, shifters, and control logic circuits), the additional time required to perform the rounding determination in some cases, such as where both addends contribute sticky bits, may in some designs be enough to require an additional clock cycle for the x87 FPU to execute a floating point add instruction or the clock cycle to be undesirably lengthened.
One solution to the problem is to have the FPU execute floating point addition instructions in a variable number of clock cycles. However, this solution is undesirable with respect to instruction scheduling, particularly within a superscalar, out-of-order execution microprocessor. Another solution is to simply take the same greater number of clock cycles (four in the example above) to execute all floating point addition instructions, regardless of the set of conditions. However, this solution is obviously not a high performance solution.
Accordingly, what is needed is a solution that generates correct results of an x87 floating point addition instruction in cases where the rounding determination is relatively long, such as where both addends contribute sticky bits to the rounding determination, and yet does not penalize the time to execute an x87 floating point addition instruction in cases where the rounding determination is relatively short, such as where only one addend contributes sticky bits to the rounding determination.